Kernel Metadata Declaration — on demand
ISO 26324 asks a DOI Registration Agency to produce a Kernel Metadata Declaration for every DOI it issues. Give any DOI: its public record becomes a record in the Smart Scholars DOI Metadata Format 1.0, checked against every rule, and declared as the Kernel XML.
✓ Meets every rule of the format
The record below is complete and every controlled value is a DOI Attribute Value Set 2.3 spelling. The Declaration on the right follows DOIMetadataKernel.xsd element by element.
What the DOI identifies
A Comprehensive Analysis of 32nmtechnology of Ladner Fischer Adder usingCMOSLogic,PTL,andDPTLFocusing onPower
10.46243/jst.2024.v9.i4.pp50-58 · JournalArticle — an article in a journal · Digital · Visual · Language · en
Published 2024-04-01
Part of Journal of Science & Technology · ISSN 2456-5660 · vol. 09 · no. 04 · pp. 50–58
Principal agents
- K.Srilatha (author → Author)
- K.SriLakshmi Amulya (author → Author)
- G.Amara Sowjanya (author → Author)
- M.Hima (author → Author)
- Longman Publishers (publisher → Publisher)
Also in the record, outside the Kernel: the abstract, the licence, 4 links, 10 references. Source: Crossref (member 25296), registered 2026-09-18, last deposited 2026-09-21.
System metadata — ISO 26324:2025, Annex B · DOI Handbook 10.1
Each element by the standard's name and the Handbook's (in grey), read off the record.
| DOI Name DOI name | 10.46243/jst.2024.v9.i4.pp50-58 |
| Referent Type referentType | Creation |
| Referent Sub-Type referentSubType | JournalArticle — an article in a journal |
| Referent Name(s) referentName(s) | A Comprehensive Analysis of 32nmtechnology of Ladner Fischer Adder usingCMOSLogic,PTL,andDPTLFocusing onPower (PrincipalTitle, en) |
| Basic Metadata basicMetadata | author: K.Srilatha author: K.SriLakshmi Amulya author: G.Amara Sowjanya author: M.Hima publisher: Longman Publishers published: 2024-04-01 part of: Journal of Science & Technology · ISSN 2456-5660 · vol. 09 · no. 04 · pp. 50–58 language: en form: Digital · Visual · Language |
| Referent Identifier(s) alternateIdentifier(s) | none besides the DOI |
| Registration Authority registrationAuthorityCode | Crossref — issued by Crossref (member 25296); held here as a copy |
| Created Date issueDate | 2026-09-18 |
| relatedIdentifiers | none needed — the descriptive metadata is in this record |
The record
{
"format": "smartscholars-doi-metadata/1.0",
"doi": "10.46243/jst.2024.v9.i4.pp50-58",
"referent": "Creation",
"type": "JournalArticle",
"structural_type": "Digital",
"modes": [
"Visual"
],
"characters": [
"Language"
],
"titles": [
{
"value": "A Comprehensive Analysis of 32nmtechnology of Ladner Fischer Adder usingCMOSLogic,PTL,andDPTLFocusing onPower",
"type": "PrincipalTitle",
"lang": "en"
}
],
"identifiers": [
{
"type": "DOI",
"value": "10.46243/jst.2024.v9.i4.pp50-58"
}
],
"agents": [
{
"role": "author",
"name": {
"given": "",
"family": "K.Srilatha"
},
"sequence": "first"
},
{
"role": "author",
"name": {
"given": "K.SriLakshmi",
"family": "Amulya"
},
"sequence": "additional"
},
{
"role": "author",
"name": {
"given": "G.Amara",
"family": "Sowjanya"
},
"sequence": "additional"
},
{
"role": "author",
"name": {
"given": "",
"family": "M.Hima"
},
"sequence": "additional"
},
{
"role": "publisher",
"name": {
"org": "Longman Publishers"
}
}
],
"dates": {
"published": "2024-04-01",
"date_type": "PublicationDate",
"online": "2024-04-01"
},
"language": "en",
"container": {
"type": "Journal",
"titles": [
{
"value": "Journal of Science & Technology",
"type": "PrincipalTitle"
}
],
"identifiers": [
{
"type": "ISSN",
"value": "2456-5660",
"medium": "electronic"
}
],
"volume": "09",
"issue": "04",
"pages": {
"first": "50",
"last": "58"
}
},
"links": [
{
"url": "https://www.jst.org.in/index.php/pub/article/view/1056",
"return_type": "text/html",
"primary": true
},
{
"url": "https://www.jst.org.in/index.php/pub/article/download/1056/923",
"purpose": "text-mining",
"return_type": "application/pdf"
},
{
"url": "https://www.jst.org.in/index.php/pub/article/download/1056/4012",
"purpose": "text-mining",
"return_type": "application/xml"
},
{
"url": "https://www.jst.org.in/index.php/pub/article/view/1056/923",
"purpose": "similarity-checking"
}
],
"abstract": {
"value": "Adders are designed as essential components in digital signal processing and VLSI technologies. Among them, parallel prefix adders offer significant speed advantages over traditional binary adders for various electronic applications. This paper explores the design of a 4-bit Ladner-Fischer adder using different technologies like CMOS, pass transistor logic, and double pass transistor logic to achieve a more efficient use of low power. These implementation results demonstrate that the Ladner Fischer adder, designed with CMOS, PTL, and DPTL, has reduced power consumption The simulation was performed using Dsch3 and the Microwind 3.1 tool.",
"lang": "en"
},
"license": {
"url": "https://creativecommons.org/licenses/by/4.0/",
"start": "2024-04-01",
"applies_to": "vor"
},
"references": [
{
"key": "ref1",
"doi": "10.1109/iconstem56934.2023.10142406",
"unstructured": "“An Efficient Design and Performance Analysis ofNovel 8 Bit Modified Wallace Multiplier Using KoggeStone Adder (KSA) in Comparison with Ripple carry adder(RCA)”. (IEEE Access, 2023)"
},
{
"key": "ref2",
"unstructured": "“Design and Parametric Evaluation of Kogge Stone Adder using CMOS and PTL in terms of Delay AND Area”.(Published in June 2022)"
},
{
"key": "ref3",
"unstructured": "“Analysis of Parallel Prefix Adders with Low Power andHigher Speed “. (Published in 2022)"
},
{
"key": "ref4",
"doi": "10.1109/icicv50876.2021.9388489",
"unstructured": "”Design an Area Efficient Kogge Stone Adder using Pass Transistor Logic “. (Published in March 2021)"
},
{
"key": "ref5",
"doi": "10.1109/iccs1.2017.8325971",
"unstructured": "S. Daphni and K. S. V. Grace, “A review analysis of parallel prefix adders for better performance in VLSI applications,” 2017 IEEE International Conference on Circuits and Systems (ICCS), 2017,pp. 103-106"
},
{
"key": "ref6",
"unstructured": "Ahmet SERTBAS and R. Selami OZBEY, “APerformance analysis of classified binary adderarchitectures and the VHDL Simulations”, Journal of Electrical & Electronics Engineering,2004, vol:4, PP:1025-1030"
},
{
"key": "ref7",
"doi": "10.25046/aj040213",
"unstructured": "S. Daphni, K. S. Vijula Grace, “Design andAnalysis of 32-bit Parallel Adders for Low Power VLSIApplications” in Advance in Science, Technology andEngineering Systems Journal Vol. 4, No. 2, PP: 102-106(2019)"
},
{
"key": "ref8",
"doi": "10.1109/cicn.2016.117",
"unstructured": "C. N. Shilpa, K. D. Shinde and H. V. Nithin, “Design, Implementation and Comparative Analysis of Kogge Stone Adder Using CMOS and GDI Design:A VLSI Based Approach,” 2016 8th International Conference on Computational Intelligence and Communication Networks (CICN), 2016, pp.570-574"
},
{
"key": "ref9",
"doi": "10.1109/icdcsyst.2018.8605064",
"unstructured": "R. M. James and A. Ravindran, “Review of Full Adder Performance Analysis Using Kogge Stone Adder and Magnetic Tunnel Junction,” 2018 4th International Conference on Devices, Circuits andSystems (ICDCS), 2018, pp. 8490"
},
{
"key": "ref10",
"doi": "10.1016/b978-0-12-415992-1.00009-2",
"unstructured": "B. David, Kirk Wen-mei W. Hwu, “Chapter 9–Parallel Patterns: Prefix Sum: An Introduction to Work Efficiency in Parallel Algorithms”, in Programming Massively Parallel Processors (SecondEdition), PP: 197-216(2013)"
}
],
"record": {
"registrant": "Longman Publishers",
"registered": "2026-09-18",
"updated": "2026-09-21",
"issue_number": 1,
"source": "crossref-api",
"source_agency": "Crossref (member 25296)"
}
}The Kernel Metadata Declaration
DOIMetadataKernel.xsd · namespace http://www.doi.org/2010/DOISchema · Attribute Value Sets 2.3 · draft — the agency's DOI name is filled in on accreditation
<?xml version="1.0" encoding="UTF-8"?>
<!-- DRAFT declaration: Smart Scholars is not yet a DOI Registration Agency. registrationAgencyDoiName is a marker (10.0/ is no RA's prefix) and is filled in on accreditation. -->
<kernelMetadata xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.doi.org/2010/DOISchema https://www.doi.org/doi_schemas/DOIMetadataKernel.xsd" xmlns="http://www.doi.org/2010/DOISchema">
<referentDoiName>10.46243/jst.2024.v9.i4.pp50-58</referentDoiName>
<primaryReferentType>Creation</primaryReferentType>
<registrationAgencyDoiName>10.0/smart-scholars-draft</registrationAgencyDoiName>
<issueDate>2026-10-04</issueDate>
<issueNumber>1</issueNumber>
<referentCreation>
<name primaryLanguage="en">
<value>A Comprehensive Analysis of 32nmtechnology of Ladner Fischer Adder usingCMOSLogic,PTL,andDPTLFocusing onPower</value>
<type>PrincipalTitle</type>
</name>
<identifier>
<nonUriValue>10.46243/jst.2024.v9.i4.pp50-58</nonUriValue>
<uri returnType="text/html" doesContentNegotiation="true">https://doi.org/10.46243/jst.2024.v9.i4.pp50-58</uri>
<type>DOI</type>
</identifier>
<identifier>
<uri returnType="text/html">https://www.jst.org.in/index.php/pub/article/view/1056</uri>
<type>URI</type>
</identifier>
<identifier>
<uri>https://www.jst.org.in/index.php/pub/article/download/1056/923</uri>
<type>URI</type>
</identifier>
<identifier>
<uri returnType="application/xml">https://www.jst.org.in/index.php/pub/article/download/1056/4012</uri>
<type>URI</type>
</identifier>
<identifier>
<uri>https://www.jst.org.in/index.php/pub/article/view/1056/923</uri>
<type>URI</type>
</identifier>
<structuralType>Digital</structuralType>
<mode>Visual</mode>
<character>Language</character>
<type>JournalArticle</type>
<principalAgent>
<name>
<value>K.Srilatha</value>
<type>PrincipalName</type>
</name>
<role>Author</role>
</principalAgent>
<principalAgent>
<name>
<value>K.SriLakshmi Amulya</value>
<type>PrincipalName</type>
</name>
<role>Author</role>
</principalAgent>
<principalAgent>
<name>
<value>G.Amara Sowjanya</value>
<type>PrincipalName</type>
</name>
<role>Author</role>
</principalAgent>
<principalAgent>
<name>
<value>M.Hima</value>
<type>PrincipalName</type>
</name>
<role>Author</role>
</principalAgent>
<principalAgent>
<name>
<value>Longman Publishers</value>
<type>PrincipalName</type>
</name>
<role>Publisher</role>
</principalAgent>
<linkedCreation>
<name>
<value>Journal of Science & Technology</value>
<type>PrincipalTitle</type>
</name>
<identifier>
<nonUriValue>2456-5660</nonUriValue>
<type>ISSN</type>
</identifier>
<referentCreationRole>Part</referentCreationRole>
<referentCreationSequenceIdentifier>
<value>09</value>
<type>VolumeNumber</type>
</referentCreationSequenceIdentifier>
<referentCreationSequenceIdentifier>
<value>04</value>
<type>IssueNumber</type>
</referentCreationSequenceIdentifier>
<referentCreationSequenceIdentifier>
<value>50-58</value>
<type>PageNumber</type>
</referentCreationSequenceIdentifier>
</linkedCreation>
<language>en</language>
<languageOfReferentContent>
<language>en</language>
<languageOfReferentContentType>Original</languageOfReferentContentType>
</languageOfReferentContent>
<creationDate>
<date>2024-04-01</date>
<creationDateType>PublicationDate</creationDateType>
</creationDate>
</referentCreation>
</kernelMetadata>
