Kernel Metadata Declaration — on demand

What the DOI identifies

A comparative analysis of 128 bytes SRAM architecture using Single ended three and six transistor SRAM cells

10.46243/jst.2022.v7.i02.pp21-29 · JournalArticle — an article in a journal · Digital · Visual · Language · en

Published 2022-07-03

Part of Journal of Science & Technology · ISSN 2456-5660 · vol. 7 · no. 2 · pp. 21–29

Principal agents

• B.N. Srinivasarao B.N. Srinivasarao (author → Author)
• Longman Publishers (publisher → Publisher)

Also in the record, outside the Kernel: the abstract, the licence, 4 links, 10 references. Source: Crossref (member 25296), registered 2024-02-16, last deposited 2026-09-17.

⬇ Record (JSON) ⬇ Declaration (XML)

System metadata — ISO 26324:2025, Annex B · DOI Handbook 10.1

Each element by the standard's name and the Handbook's (in grey), read off the record.

The record

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    "abstract": {
        "value": "Static RAM architecture is an important part in the digital data processing devices like DSP’s Micro Processors and Embedded systems for general purpose or specific purpose applications. Demand of manufacturing compact devices are increasing day by day, to make the compact devices the design of internal circuits area also should be reduced. This will in turn reduces the overall size of the device. In this paper two 128 bytes SRAM architectures are implemented with conventional six transistors SRAM cell and single ended three transistor SRAM cell from the scratch to layout level. The designs are compared in terms of power consumption, area, and speed with 45nm technology. The implemented design area is reduced by 57.14% with 92.37% reduced power consumption and with 89.98% improved performance.",
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            "key": "ref1",
            "doi": "10.1109/les.2017.2750140",
            "unstructured": "Samira Ataei and James E “A 64 kB Approximate SRAM Architecture for Low-Power Video Applications,” IEEE Embedded Systems Letters 2017"
        },
        {
            "key": "ref2",
            "unstructured": "B.N. Srinivasa Rao, Ch. Jhansi “Design And Analysis of SRAM Array Architectures”, International Journal of Management, Technology And Engineering, Volume 9, Issue 1, January 2019"
        },
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            "key": "ref3",
            "doi": "10.1109/tcsvt.2011.2105550",
            "unstructured": "I. J. Chang et al., “A priority-based 6T/8T hybrid SRAM architecture for aggressive voltage scaling in video applications,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 21, pp. 101–112, Feb 2011"
        },
        {
            "key": "ref4",
            "doi": "10.1109/tvlsi.2009.2031468",
            "unstructured": "M. Cho et al., “Reconfigurable SRAM architecture with spatial voltage scaling for low power mobile multimedia applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, pp. 161–165, Jan 2011"
        },
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            "unstructured": "Jesal P. Gajjar, Aesha S. Zala, Sandeep K. Aggarwal “Design and Analysis of 32 bit SRAM architecture in 90nm CMOS Technology”, International Research Journal of Engineering and Technology, volume 3, issue 4, April 2016"
        },
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            "key": "ref6",
            "doi": "10.1109/tvlsi.2015.2450500",
            "unstructured": "Kyoman Kang, Younghwi Yang, Juhyun Park, Kiryong Kim, and Seong-Ook Jung “Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation,” IEEE Transactions on Very Large Scale Integratin (VLSI) Systems 2015"
        },
        {
            "key": "ref7",
            "doi": "10.1109/tvlsi.2014.2377518",
            "unstructured": "Sied Mehdi Fakhraie and Ghasem Pasandi “A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations,” IEEE Transactions on VLSI Systems 2014"
        },
        {
            "key": "ref8",
            "doi": "10.1109/jssc.2008.2011972",
            "unstructured": "Ik Joon Chang, Jae-Joon Kim, Sang Phill Park and Kaushik Roy (2009), ‘A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS’, IEEE Journal of Solid-state Circuits, Vol. 44, No. 2"
        },
        {
            "key": "ref9",
            "doi": "10.35940/ijrte.d4264.118419",
            "unstructured": "M. Madhumalini, B. Saranraj “Design of Low Power Memory Architecture using 10t SRAM Array”, International Journal of Recent Technology and Engineering (IJRTE) ISSN: 2277- 3878, Volume-8 Issue-4, November 2019"
        },
        {
            "key": "ref10",
            "doi": "10.36227/techrxiv.173687647.77078261/v1",
            "unstructured": "G. Torrens (Member, IEEE), B. Alorda (Member, IEEE), C. Carmona, D. Malagón-Periánez, J. Segura (Member,IEEE), S.A. Bota (Senior Member, IEEE) “A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors”, IEEE Transactions on Emerging Topics in Computing, 2017"
        }
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The Kernel Metadata Declaration

DOIMetadataKernel.xsd · namespace http://www.doi.org/2010/DOISchema · Attribute Value Sets 2.3 · draft — the agency's DOI name is filled in on accreditation

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